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NXP Semiconductors
Table 3.
Pin description …continued
PCA9533
4-bit I 2 C-bus LED dimmer
Symbol
SCL
SDA
V DD
Pin
6
7
8
Description
serial clock line
serial data line
supply voltage
6. Functional description
Refer to Figure 1 “Block diagram of PCA9533” .
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9533/01 is shown in Figure 4 and the address of
PCA9533/02 is shown in Figure 5 .
slave address
slave address
1
1
0
0
0
1
0
R/W
1
1
0
0
0
1
1
R/W
002aae627
002aae628
Fig 4.
PCA9533/01 slave address
Fig 5.
PCA9533/02 slave address
The last bit of the address byte de?nes the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9533, which will be stored in the Control register.
0
0
0
AI
0
B2
B1
B0
Reset state: 00h
Auto-Increment
flag
register address
002aad744
Fig 6.
Control register
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment (AI) ?ag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contents of these bits will rollover to ‘000’ after the last register
is accessed.
When Auto-Increment ?ag is set (AI = 1) and a read sequence is initiated, the sequence
must start by reading a register different from the INPUT register (B2 B1 B0 ≠ 0 0 0).
Only the 3 least signi?cant bits are affected by the AI ?ag. Unused bits must be
programmed with zeroes.
PCA9533_3
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2009
4 of 24
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